? at a glance ? product brief s3165 sonet/sdh/fec/fc/ge/hdtv/dtv/d1/escon multirate 16-bit transceiver empowering intelligent optical networks 1 pb2015_v1.01_02/08/06 description the s3165 sonet/ sdh/ gigabit ethernet/ fibre channel/ hdtv/ escon/ dtv/ d1 transceiver is one of the latest additions to amcc?s oc-48 product family. the s3165 device provides fully integrated serialization/de-serialization capabilities for low power sonet/ sdh/ gigabit ethernet/ fibre channel/ hdtv/ escon/ dtv/ d1 applications. the device performs all necessary parallel- to-serial and serial-to-parallel functions in conformance with sonet/ sdh/ gigabit ethernet/ fibre channel/ hdtv/ escon/ dtv/ d1 transmission standards. the standard operating range is from 2.125 gbps to 3.00 gbps and the device incorporates multiple dividers to cover the rates for the protocols listed under general features. figure 1, system block diagram , shows a typical network application. overview the s3165 can be used to implement the front end of sonet/ sdh/ gigabit ethernet/ fibre channel/ hdtv/ escon/ dtv/ d1 equipment which consists primarily of the serial transmit interface and the serial receive interface. the system timing circuitry consists of a high- speed phase detector, clock dividers, and clock distribution. the device utilizes on-chip clock synthesis pll components that allow the use of a slower external clock reference, 155.52 mhz (or equivalent rate), in support of existing system clocking schemes. the low-jitter, 16-bit differential lvpecl/lvds data path or single-ended lvpecl option interfaces guarantee compliance with the bit-error rate requirements of the telecordia and itu-t standards. s4801 amazon sts-48c pos/atm sonet mapper s4802 missouri sonet/sdh sts-48/stm- 16 framer/ pointer processor s4804 rhine sts-48 sonet/sdh framer and pos/atm mapper s4805 danube sonet/sdh sts-48/stm- 16 framer/ pointer processor s19201 indus sts-192 sonet/sdh inter- leaver/ disinterleaver general features ? operational from 2.125 gbps to 3.00 gbps ? supports: - oc-48 with or w/o fec - oc-24 with or w/o fec - oc-12 with or w/o fec - oc-3 with or w/o fec - hdtv (1.485 gbps) -d1 (1.38 gbps) - fibre channel (1062 mbps) - 2 x fibre channel (2.124 gbps) - gigabit ethernet (1.25 gbps) - dtv (143.18 mbps) - escon (200 mbps) ? 650 mw typical power ? integrated clock data recovery ? on-chip high-frequency pll for clock generation and clock recovery ? reference frequency of 155.52 to 166.63 mhz ? rx and tx reference selectable ? interface to lvcmos/lvttl logic ? internal input termination option built-in ? 16-bit differential lvpecl/lvds data path or single-ended lvpecl option continued on next page... figure 1. system block diagram amcc missouri s4802, framer or asic amcc s3165 amcc s3165 orx otx otx orx amcc missouri s4802, framer or asic 16 16 16 16
6290 sequence drive ? san diego, ca 92121 ? tel: 858 450-9333 ? fax: 858 450-9885 ? http://www.amcc.com amcc reserves the right to ma ke changes to its products, or to discontinue any product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied upon is current. amcc is a registered trademark of applied micro circuits corporation. copyright ? 2006 applied micro circuits corporation. all rights reserved. distribute only on a need-to-know basis, and subject to applicable nda. not to be disclosed to or used by any other person with out prior authorization. product brief s3165 sonet/sdh/fec/fc/ge/hdtv/dtv/d1/escon multirate 16-bit transceiver pb2015_v1.01_02/08/06 2 empowering intelligent optical networks confidential and proprietary the sequence of operations is as follows: transmitter operations 1. 16-bit parallel input 2. parallel-to-serial conversion 3. serial data output receiver operations 1. clock and data recovery from serial input 2. serial-to-parallel conversion 3. 16-bit parallel output internal clocking and control functions are transparent to the user. ? 196 pbga package ? diagnostic and line loopback mode ? support serial loop timing mode ? lock detect ? signal detect input with polarity select ? low jitter lvpecl/lvds interface ? internal fifo to decouple transmit clocks ? dual 1.2 v and 3.3 v/2.5v supply ? complies with telcordia and itu- t specifications ? built-in self test transmitter features ? reference frequency of 155.52 mhz (or equivalent rate) ? 155.52 mhz (or equivalent rate) clock output ? internal, self-initializing fifo to decouple transmit clocks receiver features ? recovers clock from data ? low-jitter cml differential or single-ended serial interface ? reference frequency of 155.52 mhz (or equivalent rate) applications ? sonet/sdh-based transmission systems ? sonet/sdh modules ? wavelength division multiplexing (wdm) ? section repeaters ? add drop multiplexers (adm) ? broad-band cross-connects ? fiber optic terminators ? fiber optic test equipment figure 2. s3165 ordering information prefix package device s ? integrated circuit 3165 pb - 196 pbga x xxxx xx prefix device package temperature grade i - industrial x temp
|
